UALink publishes four specs, formalising the open answer to NVLink
The 115-member consortium ratifies In-Network Compute, a UCIe 3.0-compliant Chiplet spec, Manageability and a split 200G physical layer, scale-up fabric as an open standard
Summary
The UALink Consortium, over 115 members, board led by AMD, Apple, AWS, Cisco, Google, HPE, Intel, Meta, Microsoft and Synopsys, ratified four specifications on 7 April 2026, hardening the open scale-up fabric meant to rival Nvidia's proprietary NVLink. UALink Common 2.0 adds In-Network Compute (computation inside the fabric, chasing NVLink's collective-operation edge); the 200G Data Link/Physical Layers were split out so speeds can advance without reopening the protocol; Manageability 1.0 adds gNMI/YANG/Redfish control planes; and Chiplet 1.0 is fully compliant with the UCIe 3.0 spec, stitching UALink into existing chiplet SoCs. The 1.0 line links up to 1,024 accelerators per pod at 200Gbps per lane; first silicon from AMD, Intel and Astera Labs is due late 2026.
By the numbers
- 4, specifications ratified 7 April 2026 (Common 2.0, 200G DL/PL 2.0, Manageability 1.0, Chiplet 1.0).
- 115+, UALink member companies.
- 1,024, accelerators linkable per pod under the 200G spec.
- 200 Gbps, per-lane throughput (PHY based on IEEE P802.3dj).
- Late 2026, first UALink hardware (AMD, Intel, Astera Labs).
Why it matters
Scale-up interconnect is where Nvidia's moat is widest. An open, multi-vendor fabric that hits 1,024-accelerator pods, folds compute into the network, and snaps into UCIe chiplets lets AMD, Intel and the hyperscalers' custom silicon compete on equal fabric terms, or keeps them dependent on NVLink Fusion if it stalls in hardware.
What to watch
- Whether late-2026 UALink silicon ships on schedule and interoperates across vendors.
- Adoption of In-Network Compute vs Nvidia's SHARP/NVLink collective offload.
- Chiplet 1.0 uptake as the UCIe-compliant die-to-die path for non-Nvidia accelerators.