hardware/industry desk

Details CXMT's ~¥29.5B ($4.2B) Shanghai STAR Market IPO at a valuation up to ~$42B, laying out a path to profitability off a tight global memory market. Frames the listing as capital to scale DDR5/LPDDR5X capacity precisely when the incumbents' price discipline leaves room for a fourth player.

“CXMT aims to raise ~$4.2B to expand DDR5 capacity as global DRAM demand skyrockets, targeting a valuation up to $42B.”

Reports Intel has two prospective 14A customers sampling at the 0.5 PDK milestone, with commitments expected in H2 2026, and crucially, zero fully committed external 14A customers as of now. Frames 14A as the make-or-break node: 18A proves the comeback, 14A has to pay for it with outside logos.

“Intel has two prospective 14A customers sampling, but zero fully committed external 14A customers; commitments are expected in the second half of 2026.”

Reports SMIC on track for 5nm pilot/mass-production this year for Huawei, achieved via DUV multi-patterning without EUV. Stresses the cost penalty: yields estimated at 30-40% versus TSMC's 80%+, sustained only because Beijing treats advanced logic as national security rather than a profit centre.

“SMIC targets 5nm via DUV multi-patterning at an estimated 30-40% yield, viable only because Beijing subsidises it as national security.”

Maps the multi-fab N2 ramp alongside CoWoS and SoIC advanced-packaging expansion, arguing the real constraint on AI silicon is packaging and N2 allocation, not raw wafer starts. Frames Arizona acceleration as TSMC de-risking geographic concentration while customers absorb the cost premium.

“The N2 ramp is multi-fab; CoWoS and SoIC packaging, not wafer starts, are the uncorking bottleneck for AI silicon.”